The article presents a memory testing strategy used in BIST technology based on symmetric memory tests. The symmetric memory testing technique ensures that the testing process is carried out in an extremely efficient and fast manner. Its use allows for a reduction in the complexity of the testing process by approximately 30% compared to the standard transparent testing method based on a reference signature. This fact is of extreme importance when considering the current and future sizes of memory used.
Continuous technological development is causing the market for system-on-chip (SoC) and embedded systems to grow at a very fast pace (99% of all currently produced processors are intended for embedded and real-time systems [9,10, 13]). This development leads to an increasing demand for more reliable and fault-tolerant semiconductor memories. It should be noted that in current system-on-chip designs, memory occupies over 50% of the entire silicon area of the SoC, and it is predicted that in the near future this size will increase to 90% [2]. Additionally, system-on-chip and embedded systems operate as mission-critical systems. This application makes the process of testing all components included in these systems, including memory, which is an important building block of their construction, very significant. To ensure the proper operation of critical systems, testing should take place not only during the production phase but also during their operation. (…)
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Source: Czasopismo Logistyka