The article presents issues related to computer-aided specification of railway traffic control devices using hardware description languages. A review of currently used methods for describing railway traffic control devices and systems indicates that there is no single method capable of providing a uniform platform for describing all types of discrete control systems. Furthermore, most of the methods currently in use do not allow for computer-aided support during the specification and verification stages of the operation algorithms for such systems. It has been shown that applying hardware description languages for this purpose creates a uniform platform for the specification and verification of railway traffic control devices, while also allowing for static and dynamic verification of the description’s correctness using computer-aided tools such as logic simulators. Using the example of the specification of a single-section line block operation algorithm in VHDL, both the capabilities of the Active-HDL package and the process of computer-aided specification and verification of the designed specialized system are presented.Application of hardware description languages in specification of railway traffic control devices
Abstract
The article presents several issues concerning computer aided specification of railway traffic control devices using hardware description languages. The review of currently used description methods of railway traffic control devices and systems indicates that the method which could ensure a uniform platform for description of all kinds of discrete control systems does not exist. In addition, the majority of description methods currently used do not allow the use of computer support at the stage of specification and verification of operation algorithms of this type of systems. It is shown that application of hardware description languages for this purpose comprises a uniform platform for specification and verification of railway traffic control devices, which additionally allows static and dynamic verification of correctness of this description with the use of computer support in the form of logic simulators. On the example of specification of one-section line block operation algorithm in VHDL, both the possibilities of
Active-HDL package as well as the process of computer supported specification and verification of the designed specialized system are presented. (…)
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Source: Logistyka Magazine 4/2012