The article presents the results of simulation studies comparing the effectiveness of RAM fault detection using the signature analysis method and the proposed methods for compacting the system’s response to a test.1. INTRODUCTION
Currently, the complexity of digital integrated circuits doubles on average every year and a half.
The increase in complexity also leads to higher expectations regarding broad functionality, operating speed, and short implementation times for new solutions.
Meeting high quality requirements, including ensuring an adequate level of yield and reliability, involves the necessity of performing validation, known as testing. It is becoming an indispensable element not only of the production phase but also of operation. Memory systems, being an important part of digital systems and one of the main elements of an increasing number of computer components, must be reliable. Every year, there are more applications for memory systems where failure can have serious consequences, depending on the role of the system, ranging from user dissatisfaction and economic losses to threats to safety or human life. The demand for increasingly reliable memory systems leads to the pursuit of creating a testing process that does not affect the device’s operation and would ensure almost one hundred percent operational correctness [1, 2].
The most important goal of a test is to obtain the highest possible level of confidence in the obtained test results and the highest possible level of accuracy in the shortest possible time after exhaustive checking [1]. The requirement for easy testability of digital systems at the design stage must also be taken into account. (…)
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Source: Logistyka Magazine